1. Field of the Invention
This invention relates to monolithic analog multipliers. More particularly, this invention relates to techniques for effecting substantial improvements in performance of four quadrant analog multipliers.
2. Description of the Prior Art
Monolithic analog multipliers have been available for a number of years. Such multipliers have come to be based on a circuit concept referred to as the "Translinear Principle", as described in an article by the present inventor entitled "Translinear Circuits: A Proposed Classification", Electronic Letters, Vol. 11, No. 1, p.14, January 1975. Related disclosures are set forth in U.S. Pat. Nos. 3,589,752; 4,075,574 and 4,156,283.
It is known that a small mismatch in the emitter area in a pair of transistors (or, equivalently, a corresponding mismatch in their base-emitter voltages for the same operating conditions) will, in many translinear multiplier circuits, generate significant amounts of undesired nonlinearity, primarily of parabolic form. Typically, it requires an area mismatch of only 0.4%--or a V.sub.BE mismatch of about 100 .mu.V--to introduce 0.2% distortion. While much can be done to maintain good area delineation in IC mask-making, and other steps can be taken to reduce such mismatches as arise from thermal and doping gradients in the IC chip, a practical limit is reached in which the yield of chips having the desired accuracy becomes unacceptably low. Experience has shown that it is difficult to achieve V.sub.BE matching much better than 50 .mu.V on a routine basis, which results in distortion on the order of 0.1%. Many applications would benefit from distortion levels lower than this.